1. Field of the Invention
The present invention relates to a semiconductor memory device and a memory system, and more particularly, to a semiconductor memory device and a memory system for improving bus efficiency.
2. Description of the Related Art
Memory devices are typically developed to have a high density of integration and large capacity. Central processing units (CPU) are developed to achieve processing at high speed. The operating speed of large memory devices is usually slower than the speed of the CPUs. As a result, there arises a gap between the operating speeds of CPUs and memory devices. The slower operating speeds of memory devices restrict the overall performance of computer systems. In order to achieve speedy memory systems, high-speed memory devices must be developed and the bus efficiency thereof improved.
Synchronous DRAMs are among the fastest large-scale memory devices. However, in synchronous DRAMs, in order to reduce the number of pins, a row command (RAS) and a column command (CAS) must share an address, and a host of commands must be applied simultaneously with a chip selection signal CS. Hence, synchronous DRAMs degrade the bus efficiency of memory systems and consequently restrict the performance of memory systems.
FIG. 1 shows the pin configuration of a conventional synchronous DRAM, and FIG. 2 shows a memory system adopting the conventional synchronous DRAM of FIG. 1. In FIG. 1, only pins associated with data input and output are shown, and pins are arranged in an arbitrary order.
Referring to FIG. 1, a conventional synchronous DRAM 100 includes an input pin 11 for receiving a clock signal CK, an input pin 12 for receiving a clock enable signal CKE, an input pin 13 for receiving a chip selection signal CS, an input pin 14 for receiving a row address strobe signal RASB, an input pin 15 for receiving a column address strobe signal CASB, and an input pin 16 for receiving a write enable signal WEB. Also, the conventional synchronous DRAM 100 includes a plurality of address input pins 17-1 through 17-n for receiving addresses Ai (where i is an integer from 1 to n), and a plurality of data input and output pins 18-1 through 18-n for receiving data DQi (where i is an integer from 1 to n).
The clock enable signal CKE, the chip selection signal CS, the row address strobe signal RASB, the column address strobe signal CASB, and the write enable signal WEB are referred to as command signals, and are generated by a memory controller 23 shown in FIG. 2. The memory controller 23 also generates the clock signal CK and the addresses Ai. The data DQi is output from the memory controller 23 during a write operation, and output from the synchronous DRAM 100 during a read operation. In the conventional synchronous DRAM 100, row addresses and column addresses are received via the same input pins, that is, via the address input pins 17-1 through 17-n.
Referring to FIG. 2, a conventional memory system includes memory modules 21-1 through 21-4 on which a plurality of synchronous DRAMs M each having a pin configuration as shown in FIG. 1 are mounted, and the memory controller 23 for controlling the synchronous DRAMs M. In FIG. 2, RASB0, CASB0 and CS0 are for the memory module 21-1, RASB1, CASB1 and CS1 are for the memory module 21-2, RASB2, CASB2 and CS2 are for the memory module 21-3, and RASB3, CASB3 and CS3 are for the memory module 21-4.
FIG. 3 is a timing diagram illustrating a protocol used in the conventional memory system shown in FIG. 2 during a read operation; in particular, when data are consecutively read from memory modules 21-1 and 21-2 among the memory modules shown in FIG. 2.
In FIG. 3, it is assumed that tRCD, that is, the time of activation of RASB (that is, the transition from a logic xe2x80x9chighxe2x80x9d to a logic xe2x80x9clowxe2x80x9d) to the time of activation of CASB, is two clock cycles (2T), that a column address strobe latency CL is two clock cycles (2T), and that a burst length BL is two clock cycles (2T).
However, in the conventional memory system shown in FIG. 2, when data is read from the two memory modules 21-1 and 21-2, there exists a time period in which there is no data on a data bus, such as during a clock cycle T8 as shown in FIG. 3. During such time, no command is issued in the conventional memory system and a xe2x80x9cbubblexe2x80x9d clock cycle T8 has to be added. Thus, the bus efficiency is degraded and the performance of the memory system is restricted. If the bubble cycle T8 is removed by advancing one clock cycle, it can be seen from FIG. 3 that a column address CA1 for the memory module 21-1 and a row address RA2 for the memory module 21-2 must be concurrently applied. According to the conventional memory design and protocol, the column address lines are shared with the row address and application of concurrent CA1 and RA2 addresses will result in an erroneous read operation. A need therefore exists for a semiconductor memory device having improved bus efficiency.
The present invention provides a semiconductor memory device comprising a clock input pin for receiving a clock signal; a first chip selection signal input pin for receiving a first chip selection signal for a row address strobe from the memory controller; a second chip selection signal input pin for receiving a second chip selection signal for a column address strobe from the memory controller; a row command input pin for receiving a row command from the memory controller; a column command input pin for receiving a column command from the memory controller; a plurality of row address input pins for receiving row addresses from the memory controller; and a plurality of column address input pins for receiving column addresses from the memory controller, wherein the row command and the column command are received in response to two consecutive edges of the clock signal.
The first data of the first chip selection signal received in response to the first edge of the clock signal is recognized as a chip selection signal, and the second data of the first chip selection signal received in response to the second edge next to the first edge is recognized as a row command. The first data of the second chip selection signal received in response to the first edge of the clock signal is recognized as a chip selection signal, and the second data of the second chip selection signal received in response to the second edge of the clock signal, which is next to the first edge of the first signal, is recognized as a column command.
The present invention provides a memory system having memory modules on which a plurality of semiconductor memory devices are mounted, and a memory controller for controlling the semiconductor memory devices, wherein each of the semiconductor memory devices separately includes: a first chip selection signal input pin for receiving a first chip selection signal for a row address strobe; and a second chip selection signal input pin for receiving a second chip selection signal for a column address strobe, wherein the first and second chip selection signals are generated by the memory controller and transmitted to each of the memory modules via different bus lines.
Each of the semiconductor memory devices further comprises a row command input pin for receiving a row command; and a column command input pin for receiving a column command, wherein a bus line for transmitting the row command is separated from a bus line for transmitting the column command.
Each of the semiconductor memory devices further comprises a plurality of row address input pins for receiving row addresses; and separately a plurality of column address input pins for receiving column addresses, wherein bus lines for transmitting the row addresses are separated from bus lines for transmitting the column addresses.